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EC530 54734
M.S., National Chiao Tung University, R.O.C.
Professor, Department of Computer Science and Information Engineering, National Chiao Tung University. Instructor, Department of Computer Science, National Chiao Tung University, 1972-1977. Associate Professor, Department of Computer Engineering, National Chiao Tung University, 1977-1981. Visiting Scholar, Department of Computer Science, University of Illinois at Urbana-Champaign, 1980-1981. Full Professor, Department of Computer Engineering, National Chiao Tung University, 1981-1988. Chairman, Department of Computer Engineering ,National Chiao Tung University, 1987-1988. Visiting Scholar, Department of Computer Science, Carnegie-Mellon University, 1988-1989. Full Professor, Department of Computer Science and Information Engineering, National Chiao Tung University, 1989-now. Deputy Director of Microelectronic and Information System Research Center, National Chiao Tung University, 1990-1994.
Research Interests: Computer architectures, parallel processing systems, digital system design, VLSI/CAD design. · Computer architectures · Parallel Processing System. · RISC/Superscalar System design. · VLSI System design. · Digital system design. · Multi-threaded architecture and compiler design. · Scalable multiprocessing system. · Parallelizing compiler. · Video Server Design.
1. Phi Tau Phi scholastic honor 2. Outstanding paper award from the Chinese Computer Society of ROC 1991. Paper: ``Design and Implementation of A TDS And Architecture Issues for Superscalar Design."
It aims at the investigation of share-memory multiprocessor architecture through a user-friendly interface. It is a software platform for education and research purposes. To achieve the objectives , SEESMA supports the following simulation environment:
Each sub-environment supports various options to investigate the interactions among these options. Users are provided with an X-window interface to specify system architecture and benchmarks, besides friendly on-line help. SEESMA will run simulation based on user specified architecture and output the evaluated results. Finally, users could analyze the interaction among system modules for cost/effective system design. SEESMA is a program-driven simulator consisting of a memory reference generator(front-end) and a target system simulator (back-end). The former models execution of an application program on some number of processors, while the later models system interconnect and memory hierarchy. Once the program performs memory reference, front-end sends an event to back-end. As soon as event completed, back-end signals the front-end that process can continue. As a whole, the SEESMA has been implemented by using “C” language about 30000 statements running on SUN SPARC workstation successfully, which can support to simulate and evaluate the following various kinds of multiprocessor architectures:
Currently, the second version of SEESMA has been developing for cluster-based multiprocessor architecture design.
Research Plan: My current research plan focus on the following items: 1. "Study and develop a useful Parallelizing Compilation environment", in which Nonuniform Loop Transframation and partition techniques, Data Locality Analysis, and some Parallel Schedualing Methods will be studied and developed. The target of this research field is to develop a powerful platform and and testbed for Parallelizing Compiler design. In our environment, we use "SUIF" as the kernel tools to expolre our intersting techniques and issues. Currently, we focus our research topics on some effective parallelizing methods for irregular loops, data partitioning and allocation for cluster-based multiprocessor architectures, and job or task scheduling techniques in parallelizing compiler. 2. "Study and design of scalar multiprocessor system simulation environment". This research is the extension of our previous research contributions to scalable multiprocessor system design. In this environment, we use "MINT" Package as the "Front End" part to link our back end modules such that the whole simulation tool will be more powerful and useful. Several Scalable multiprocessor system design issues, such as distributed shared memory model, clustering architecture ,directory-based as well as snoopy-based cache coherence protocol, and some new memory consistency models, eg. AOC model, are explores and evaluated in this environment. The target of this research topic is to develop a powerful platform for high performance computer architecture design. Currently, our researches also cover come important design issues on cluster-based multiprocessor architectures. 3. "Study and design of Video Server subsystem for high performance VOD (Video on Demand) application". The main research tasks include to develop a video server tester and design a storage model for video data as well as to propose some scheduling strategies for real-time video data retrieval. Moreover, we also plan to design hard disk self-healing and fault-tolerance approaches for predictive and unpredictive failures in video server.In this field, the disk arrays will be our storage subsystem platform. Until now, some important software modules have been developed in this platform. The whole configuration of our environment can be shown in the following diagram:
Currently, we are continuously developing the environment to be a powerful and useful prototype for VOD research, education, and industrial technology transfer purposes. The above research items have been investigated by the following related projects: 1. Study of System Architecture Design for Scalable Multiprocessors (III) (Principal Investigator of integrated Project, including 4 related Projects, sponsored by NSC, 1997-1998 ) 2. Study and Implementation of Simulation Environment for Scalable Multiprocessors (III)(principal investigator, sponsored by NSC,1997-1998 ) 3. Design and Implementation of Video Server Tester and Hand Disk self-healing Systems (III)(principal Investigator, Coinvestigator with Prof. S.Y. Lee, sponsored by NSC, 1997-1998.)
A. Referred Papers [1]. C. Chen, “A Study and Implementation of Operating System and Drawing Program of Laboratory Computer for On-liine Electronic CKT Design “, The Proceedings of the NSC, No. 8, Part 3, May, 1975, pp.523-554. [2]. C. Chen, “A Note on Computer Oriented Synthesis of Minimum Static Hazard-Free Combinational Logic CKT “, The Journal of NCTU, Vol. 2, pp.241-252, Dec. 1976. [3]. C. Chen, “A Study and Implementation of Algorithmic Synthesis of Asynchronous Sequential Logic CKT “, Proceedings of National Science Council, Vol. 2, Apr. 1, 1978, pp.189-197. [4]. C. Chen and M. C. Sheng, “A Study of Register File Management Strategies for Variable Window Size in RISC-style Machine “, Proc. Of the National Science Council, Part A : Physical Science and Engineering, Vol.10, No.3. pp.313-323, July 1986. [5]. C. P. Chung, S. C. Jeng, H. C. Chou and C. Chen , “Design of the Dual-ALU CRISC and Its Concurrent Execution “, Journal of Information Science and Engineering, Vol.5, No.3, pp.251-274, July 1989. [6]. C. Chen et. Al. “An OR parallel Inference Model Based on Multi-RISC-style Processing System “, Journal of Information science and Engineering, Dec. 1991. [7]. R. L. Ma, C. P. Chung and C. Chen , “A Register Window Scheduling Method for Prolog”, Journal of Chinese Engineering, vol. 16, No. 6, pp. 793-806, 1993.. [8]. k. H. Wang, T. T. Hwang and C. Chen , “Overlapped Recompositions for Communication Complexity Driven Multilevel logic Synthesis, “ IECE Trans. On Information and System, Vol. E76-D, No.9, Sept. 1993, pp. 1075-1084. [9]. K. H. Wang, T. T. Hwang andC. Chen , “Technology Mapping for FPGA’s using Generalited Function Decomposition”, Journal of VLSI Design. Vol.2, No.2 1994. ( Special issue on Optimizations of VLSI Synthesis and Layout of VLSI ) [10]. K. H. Wang, T. T. Hwang and C. Chen , “Exploiting Communication Complexity for Boolean Matching,” IEEE Transactions on CAD, vol. 15, No. 10, Oct. 1996, pp. 1249-1256.. [11]. Chao-Chin Wu and Cheng Chen, “A Loop Partition Technique for Reducing Cache Bank Conflict in Multithreaded Architecture,” IEE Proceedings of Computers and Digital Techniques, Vol. 143, No. 1, Jan. 1996, pp. 30-36. [12]. G. J. Lai and C. Chen , “A New Program Model for Program Partitioning on NUMA Multiprocessor Systems,” to appear at IEE Proceedings on Computers and Digital Techniques, Vol. 143, No.6,pp.431-435. Nov. 1996. [13]. G. J. Lai and C. Chen , “Scheduling Parallel Program Tasks with Non-negligible Intertask Communications onto NUMA Multiprocessor Systems,” to appear at Journal of Parallel Algorithms and Applications. Nov. 1996. [14]. Chao-Chin Wu and Cheng Chen, “A Performance Study of Coherence Protocols and Write Caches for Parallel-multithreaded Shared-memory multiprocessors,” Journal of the Chinese Institute of Engineers,Vol. 21, No.1, pp. 33-46. 1998. [15]. Chao-Chin Wu, Der-Lin Pean, Jen-Pin Su,Jia-Rong Wu, Hsuan-Woei Huang, Jun-Long Huang,Jia-Lin Lee,Huey-Ting Chua, and Cheng Chen, “SEESMA: A Simulation and Evaluation Environment for Shared Memory Multiprocessor Architecture” to be published in at Proceedings of the NSC- Part A: Physical Science and Engineering. B. Conference Papers [1]. “The Design of A Master-slave Microcomputer System “, Proceedings of Workshop on Parallel Processing, Multiprogramming and Computer Networks, Computer Nonnumeric Algorithms and Nonnumeric Machine Architecture, Hsinchu, Taiwan, R.O.C. Jane, 1979, pp.24-46. [2]. 謝清俊, 林世釧, 陳正, “天罡檔案系統之設計”,六十八年中華民國全國計算機會議文集, 9-12至9-23頁. [3]. C. Chen , Y.Y. Lu and K. C. Yu, “Computer System for Small Laboratory Automation System”, Proceedings, of International Computer Symposium, (Vol. I), Taiwan, R.O.C. Dec. 1980, pp.637-667. [4]. 鍾乾癸, 張文昌, 陳正 合著, “一個點對點計算機網路的設計與製作”, 1982年國際計算會議論文集第二卷, 597-684頁. [5]. 鍾乾癸, 周勝鄰, 陳正 合著, “A New Multi-Access Scheme B-CSMA/CAD for Local Area Network”, 1982年國際計算會議論文集第二卷, 588-596頁. [6]. C. Chen , Wen Zen Shen, et al., Dec. 19-21, “ PLAMG: An Automatic PLA Minimizer and Generator for VLSI System Design “, Proceedings of the International Conference on Advanced Automation, Taipei, Taiwan, R.O.C., p.14-23, 1983. [7]. C. Chen , C. G. Chung et al., “A CAD Tool for Data Path and Control Signals Generation from Hardware Description Language for Digital System Design “, Proceedings of the International Conference on Advanced Automation, Taipei, Taiwan, R.O.C. , pp.73-81, Dec. 19-21, 1983. [8]. C. Chen , C. G. Chung and c. L. Lee, “CTU-CADDS: A Set of CAD Tools for Digital System Design: Framework, System Design and Implementation “, Proceedings of International Computer Symposium, Taipei, Taiwan, R.O.C., pp.411-417, 1984. [9]. J. W. Chen and C. Chen , “Design and implementation of Automatic Synthesis Tool: DPAS: Data Path Analyzer and Synthesizer “, Proceedings of International Computer Symposium, Taipei, Taiwan R.O.C. , pp.418-425, 1984. [10]. C. Chen and T. K. Duann, et al., “HDLC: A Compilation System of Hardware Description Language for Digital System Design “, International Symposium of VLSI Technology, systems and Applications, Proceedings of Technical Papers, Taipei, Taiwan, R.O.C., pp.194-198, 1985, [11]. C. Chen and Y. Z. Horny, “Design and Implementation of a Hardware Description Language for Digital System Design “, Proceedings of National Computer Symposium, R.O.C., pp.922-935, 1985. [12]. M. C. Sheng, C. Chen , W. Z. Shen, H. C. Fu and C. T. Tseng, “Design of a LISC (Limited Instruction Set Computer): A 32-bit RISC-like Processor “, Proceedings of National Computer Symposium, R.O.C., pp.308-324, 1985. [13]. Y. S. Tsai, C. L. Liang, C. Chen and W. Z. Sheng, “VLSI Design and Implementation of LISC: A 32-bit RISC-Style Processor. Part I : Control unit and Register File Subsystem “, Proceedings of ICS, pp.685-691, 1986. [14]. L. Chen, J. S. Yang, W. Z. Shneng and C. Chen , “VLSI Design and Implementation of LISC: A 32-bit RISC-style Processor Part II: Shifter, ALU and System Verification “, Proceedings of ICS, pp.685-691, 1986. [15]. C. Y. Cheng, C. Chen and H. C. Fu, “Design of LISCP: A Fast RISC-style A Prolog Machine. Part I: Instruction Set Design “, Proceedings of ICS, pp. 472-478, 1986. [16]. C. Y. Cheng, C. Chen and H. C. Fu, “Design of LISCP: A Fast RISC-style A Prolog Machine, Part II: Basic Machine Design and Performance Evaluations “, Proceedings of ICS, pp.479-485, 1986. [17]. C. Y. Cheng, C. Chen and H. C. Fu, “RPM: A Fast RISC Type Prolog Machine “, Proceedings of VLSI and Computers, 1st International Conference on computer Technology, Systems and Applications, Hamburg, May 11-15, 1987, pp. 95-98. [18]. T. T. Tsai, S. J. Baw, H. C. Fu, C. P. Chung, J.J.J. Shann and C. Chen , “VLSI Design of Fast RISC-style Prolog Machine “, Proceedings of International Symposium on VLSI Technology, Systems and Applications, May 13-15, 1987, Taiwan, R.O.C. pp.369-373. [19]. C. Chiang, T. C. Chang, Y. M . Shu, C. C. Chung, H. C. Fu, C. Chen , C. P. Chung, J. J. Shann, “A further Performance Evaluation on LISCP: A Fast RISC-style Prolog Machine “, Proceedings of National Computer Symposium, 1987, R.O.C., pp. 11-20. [20]. Tsai, S. J. Baw, C. Chen , H. C. Fu and C. P. Chung, “VLSI Design and Implementation of LISCP: A Fast RISC-style Prolog Machine “, Proceedings of National Computer Symposium, 1987, R.O.C., pp.30-39. [21]. Chung, C. C. Chiang, C. Chen , H. C. Fu and C. P. Chung, “A study of Parallel Execution Model for Prolog on A RISC-style Multiprocessor System “ Proc. of NCS, Taipei, Taiwan, R.O.C. 1987, pp. 102-111. [22]. Fu, C. Chen and C. P. Chung, et al., “A Multi-processor System for Prolog Processing”, Proceedings of the 2nd IEEE Conference on Computer Workstations, March, 1988, pp. 60-69. [23]. Chung, C. Chen , H. C. Fu, and C. P. Chung, “Design and Implementation of A Feasible Runtime Intelligent Backtracking Scheme for Prolog “, Proc. of ICS, Taipei, Taiwan, R.O.C. Dec. 1988 pp.659-664. [24]. Hsu, C. Chen , C. P. Chung and H. C. Fu, “A New And Parallel Execution Model for Prolog Forward Execution Method”, Proc. of ICS, Taipei, Taiwan, R.O.C. Dec. 1988, pp.800-805. [25]. T. C. Chang, C. Chen and C. P. Chung, “Design of LISCP-II: An Improved RISC-style Processor for Prolog”, Proc. of ICS, Dec. 1988. [26]. I. K. Chou, C. P. Chung and C. Chen , “A Dependence-based Loop Partitioning Method for Multitasking in A Vector Computer”, Proc. of ICS, Dec. 1990. [27]. C. Chen , C. P. Chung, et al., “Parallel Inference Model Based on Multi RISC-style Processing System” Proc. of the 1st Workshop on Parallel Processing, pp.221-230, Dec. 1990. [28]. C. Chen , et al., “An Intelligent Backtracking Technique Based on Dynamic Approach for High Performance RISC-style Prolog Machine” The Proceedings of NCS, Dec. 1991, pp.685-690. [29]. 陳正等, “一個追蹤導向模擬器之製作及超純量等架構設計之考慮”, 八十年全國計算會議論文集, pp. 91-98. [30]. R. L. Ma, C. P. Chung and C. Chen , “A Register File Management Method for Prolog System,” Proc. of ICS, Taichung, Taiwan, R.O.C., Dec. 1992, pp. 127-134. [31]. Y. T. Wang, C. Chen , C. L. Fang and J. C. Chang, “WBS: A Window-Based Scheduling Method for Superscalar Compilation Design,” Proc. of ICPADS, Hsinchu, Taiwan, R.O.C., Dec. 1992, pp.158-165. [32]. M. J. Lin,C. Chen , K. H. Peng and J. C. Chung, “A Study on Software Pipelining Technique for Superscalar Compiler Design,” Proc of ICPADS, Hsinchu, Taiwan, R.O.C., Dec. 1992, pp. 322-33. [33]. K. H. Wang, T. T. Hwang and C. Chen , “Restructuring Binary Recision Diagrams Based on Functional Equivalence,” Proceedings of the European Conference on Design Automation with the European Event in ASC Design, Feb. 22-25, 1993, pp.261-265. [34]. K. H. Wang, T. T. Hwang and C. Chen , “Technology Mapping for FPGA’s using Generatited Functional Recomposition,” International Conference of CAD/Graphic’93, Aug., Beijing, China, pp. 605-610. [35]. K. H. Wang, T. T. Hwang and C. Chen , “Restructuring Binary Decision Diagrams Based on Functional Equivalence,” Proc. Of EDAC-EUROASIC’93, Feb., 1993 pp.261-265. [36]. C. C. Wu and C. Chen , “A Study of Register File Management Scheme for Superscalar Processor Design with Dynamic Scheduling Scheme,” Proceedings of NSC, Vol.2, Dec. 1993, pp.924-933. [37]. C. C. Wu, C. Chen and W. Chen, “Design and Study of a Superscalar Architecture with Dynamic Instruction Scheduling,” Proceedings of NCS, Vol.2, Dec. 1993, pp. 934-943. [38]. C. L. Fang, G. J. Lai, C. H. Shan and C. Chen , “A Study on Thread Parallelization Techniques for Superscalar-based Multiprocessor Compiler Design,” Proceedings of NCS, Vol.2 , Dec. 1993, pp.944-953. [39]. C. C. Wu and C. Chen , “A Loop Partition Technique to Reduce Bank-Conflict for Cache subsystem Design in MultiThreaded Architecture,” Proceedings of ICS, Vol.1, Dec. 12-15, 1994, pp. 61-68. [40]. J. C. Shee, C. C. Wu and C. Chen , “Design of Multithreaded Architecture and Its parallel Simulation and Evaluation Environment,” Proceedings of ICS, Vol.1, Dec. 12-15, 1994, pp.69-76. [41]. C. Chen et. Al., “Enhanced Chunk Self-Scheduling: A New Self-Scheduling Scheme to Improve Execution Efficiency of Loop-Carrier Dependent Loops”, Proc. of 1995 Workshop on Distributed System Technologies & Applications, NCKU, Taiwan, ROC, July 4-6, 1995. [42]. C. Chen et al., “SEEMSAD: A Prototype of Simulation and Evaluation Environment for Multiprocessor System Architecture Design,” Proc. of 1995 Workshop on High Performance Multiprocessor System, pp.8-15, 1995. [43]. Lin-Wen You, Chao-Chin Wu, Jen-Pin Su, and Cheng Chen, “Design of a Parallel Multithreaded Processor Architecture and Implementation of Its Simulation and Evaluation Environment,” Proc. of National Computer Symposium , ROC, pp.148-155, 1995. [44]. C. Chen et al., “CPITP: A Compilation Prototype for Instruction and Thread Parallelization,” Proc. of 1995 Workshop on High Performance Multiprocessor System, pp. 144-151, 1995. [45]. D. L. Pean, G. J. Lai, etc., “EECS: An Education Environment for High Performance Computer Systems: Framework, System Design and Implementation,” 1996 Inter. Conf. on Computer Systems Technology for Industrial Applications, pp. 54-63. [46]. G. J. Lai and C. Chen , “A New Scheduling Strategy for NUMA Systems,” Proceedings of the 1996 Int. Conf. On Parallel and Distributed Systems, June 3-6, 1996, pp.222-229. [47]. Jen-Pin Su, Chao-Chin Wu “Reducing the Overhead of Migratory-Shared Access for the Linked-Based Directory Coherent Protocols in Shared Memory Multiprocessor Systems,” Proc. of ICS’96 on Computer Architecture, Kaohsiung, Taiwan, R. O. C., Dec. 19-21, 1996, pp. 160-167. [48]. Cheng Chen et al., “An Efficient Data and Computation Decomposition Technique for Nested Loop on NUMA Multiprocessor Systems,” Proc. of ICS’96 on Computer Architecture, Kaohsiung, Taiwan, R. O. C., Dec. 19-21, 1996, pp. 168-174. [49]. Der-Lin Pean, Cheng Chen. “一個有效率的不規則相依迴圈平行化技巧,” Proceedings of NCS’97, Volume 3,pp. E58-E66. [50]. Derh-Lin Pean, Chao Chin Wu, Huey-Ting Chua and Cheng Chen. “ Effective Parallelization Techniques for Non-uniform Loops” Proc. of the 21st Australasian Computer Science Conference, ACSC’98 Perth, 4-6 February 1998, pp. 393-404 C. Technical Reports [1]. 陳正, 林國貴, 1983年10月, “自ISPS高階硬體描述所設計而建立以Distributed Style架構為主之資料路徑分析器及產生器”, 工研院電子所(計算機輔助下之計算機結構之研究)第一年期末報告之一. [2]. 陳正, 鍾乾癸, 包崇華合著,1983年10月, “自ISPS高階硬體描述所設計而建立以Distributed Style架構為主之資料路徑分析器及產生器”, 工研院電子所(計算機輔助下之計算機結構之研究)第一年期末報告之二. [3]. 陳正, 陳健合著, 1983年10月, “自ISPS層面效益評估系統之研究(Intel 8080與Z-80之個案)”, 工研院電子所(計算機輔助下之計算機結構之研究)第一年期末報告之三. [4]. 陳正, 李其昌, 鄭炎慶, 周李義合著, 1993年,”一個高階I/O描述語言SLIDE之轉換器(Translator)之設計與建立”,工研院電子所(計算機輔助下之計算機結構設計之研究)第一年期末研究報告四. [5]. 陳正, 陳如薇, 1984年10月,”微結構自動合成系統之一:資料路徑之分析及產生器”,工研院電子所(計算機輔助下之計算機結構設計之研究)第二年期末報告之一. [6]. 陳正,王凡合著,1984年10月,”微結構自動合成系統之二:微程式化控制單元之分析與合成”,工研院電子所(計算機輔助下之計算機結構設計之研究)第二年期末報告之二. [7]. 陳正,曾金財,李棟村合著,1984年10月,”微程式組合及除錯系統之發展”,工研院電子所(計算機輔助下之計算機結構設計之研究)第二年期末報告之三. [8]. 陳正,曾金財,朱念祖合著,1984年10月,”微結構模擬器之設立與建立”,工研院電子所(計算機輔助下之計算機結構設計之研究)第二年期末報告之四. [9]. 陳正,李其昌,曾金財,盛敏成,周輝麟合著,1984年10月,”I/O SLIDE-like語言之模擬及評估系統之設計與建立”,工研院電子所(計算機輔助下之計算機結構設計之研究)第二年期末報告之五. [10]. 陳正,戚務慶,中華民國七十四年十二月,”基於規則方法而建立之閘矩陣佈線圖字動產生器”, 國科會七十三年度超大型積體電路計算機輔助設計系統之建立研究計畫期末研究報告之五,(NSC74-0404-E009-11). [11]. 陳正等, “提供超大型積體電路系統設計之新硬體描述語言設計及其應用之研究”,電子與資訊研究中心期末報告,民國七十五年十月(TR-MIST-85-026). [12]. 陳正,任建葳,”有關提供人工智慧之精簡指令計算機之VLSI設計的研究”,國科會七十五年度計算機輔助設計系統與超大型積體電路設計專題研究計畫期末研究報告.(NSC0204-E009-02). [13]. 陳正等,”多元處理機系統設計之研究”電子與資訊研究中心期末研究報告,民國七十六年一月.(TR-MIST-E7505). [14]. 傅心家, 陳正等,”人工智慧多處理機系統之研究”,國科會專題研究計畫成果報告.民國七十六年十月.(NSC75-0408-E009-07). [15]. 陳正 等,”以C語言為對象之RISC-Based多元處理機系統設計之研究”,電子與資訊研究中心期末技術報告,民國77年7月.(TR-MIST-E77004). [16]. 鍾崇斌, 陳正,傅心家等,”人工智慧型多處理機系統之研究”,國科會專題研究計畫成果報告.民國78年9月.(TR-MIST-E79012) [17]. 陳正, 鍾崇斌等,”高速計算機架構設計之研究”,電子與資訊研究中心期末技術報告,民國79年9月.(TR-MIST-E79012) [18]. 鍾崇斌, 陳正等,”人工智慧型多處理機系統之研究”,國科會專題研究計畫成果報告.民國78年10月.(NSC-79-0408-E009-08) [19]. 陳正 等,”基於超純量與超導管技術之高性能計算機等架構設計之研究”,工研院電通所支助下電子與資訊研究中心期末報告. 1991年8月. [20]. 陳正 等,”基於超純量與超導管技術之高性能計算機等架構設計之研究(II)”,交大電子與資訊研究中心期末報告. 1991年8月. [21]. 陳正, 謝續平,張明峰,”高性能多元處理機系統設計環境之研究(I)”,國科會期末研究報告, 1993年12月. [22]. 陳正, 謝續平,張明峰,”高性能多元處理機系統設計環境之研究(II)”,國科會期末研究報告, 1994年12月. [23]. 陳正, 謝續平,張明峰,”高性能多元處理機系統設計環境之研究(III)”,國科會期末研究報告, 1995年12月. [24]. 陳正, 吳全臨,”可延伸性多處理機系統架構設計之研究,子計劃一:可延伸性多處理機系統架構設計之研究(I)”,國科會期末研究報告,1996年12月. [25]. 陳正, 吳全臨,”可延伸性多處理機系統架構設計之研究,子計劃二:平行編譯技術及其環境之探討(II)”,國科會期末研究報告, 1996年12月. [26]. 陳正, 李素瑛,”多媒體互動式資訊系統之研發產學合作計劃,子計劃二:視頻伺服器監督管理系統之研製(I)”,國科會期末研究報告, 1997年2月. [27]. 陳正, 吳全臨,”可延伸性多處理機系統架構設計之研究, 子計畫四: 可延伸性多處理機架構模擬環境之研製與相關平行化編譯計數之探討(II)”, 國科會期末研究報告, 1997年12月. [28]. 陳正, ”多媒體互動式資訊系統之研發產學合作計劃,子計劃二:視頻伺服器監督管理系統之研製(II)”,國科會期末研究報告, 1998年2月.
Laboratory Facilities:
In this lab, we have six PCs and nine workstations, which are listed below:
(i) PC部分： CSPC1：Pentium 133 CSPC2：Pentium 120 CSPC3：Pentium 133 CSPC4：Pentium 133 CSPC5：Pentium 166 MMX CSPC6：Pentium 166 MMX
(ii) 工作站部分： CSSUN1：Sparc 10 CSSUN2：Sparc 10 CSSUN3：Sparc 10 CSSUN4：Ultra Sparc CSSUN5：Sparc 20 CSSUN6：Sparc 20 CSSUN7：Ultra Sparc CSSUN8：Ultra Sparc CSSUN9：Ultra Sparc
By using the above computing facilities, we have developed our powerful platform, SEESMA, to study the design issues of scalable multiprocessor architectures. Besides, we also use SUIF package to develop our parallelizing compiler environment on those SUN workstations.
(B) Integrated Multimedia Interactive Information System Laboratory (Room in 電子資訊研究大樓) In this lab, we have the following facilities used to support the video server platform researches:
Video Server(視訊伺服器) x 2 JukeBox(500片光碟櫃) x 1 28"TV(28吋電視機) x 12 SET TOP bus x 20
PC: Pentium Pro 180 x 2 Pentium 166 MMX x 2
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